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Platform: |
Size: 53365 |
Author: dhl1983 |
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Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写,能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: |
Size: 207924 |
Author: 上面的 |
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Description: 本文件是altera公司fpga的ip核,从国外网站下载的免费源码。-ALTERA This document is the company they simply ip nuclear, downloaded from the web free source.
Platform: |
Size: 787352 |
Author: 崔战 |
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Description: altera公司的fpga期间的所有lpm模块的快速设计,涵盖了全部的lpm ip模块-altera during the fpga all lpm module rapid design, cover all the ip module lpm
Platform: |
Size: 532693 |
Author: 江汉 |
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Description: 这是基于altera的片上处理器nios 的一个IP电话终端的设计,来源altera的电子设计文章大赛.
Platform: |
Size: 190417 |
Author: wokkoni |
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Description: altera公司的IP core,对于初学硬件描述语言,想要利用quartus软件自带的锁相环电路库函数实现自己想要的功能有些帮助-altera the IP core, for hardware description language learning, quartus want to use the software to bring their own PLL circuit to achieve the function they want to help some of the functions
Platform: |
Size: 716143 |
Author: 林德 |
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Description: altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。
Platform: |
Size: 15594 |
Author: 朱峰 |
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Description: altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以轻易实现对dm9000a网卡的控制。
Platform: |
Size: 16258 |
Author: 朱峰 |
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Description: altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以轻松控制vga的显示,十分难得哦!
Platform: |
Size: 23618 |
Author: 朱峰 |
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Description: altera的ip核, 添加后,在quartusII中可以轻松实现对i2c的控制,是fpga开发人员的必备工具之一。
Platform: |
Size: 12461 |
Author: 朱峰 |
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Description: 如何给时钟倍频或者分频,以及altera提供的IP核使用方法
Platform: |
Size: 2528 |
Author: 杨华 |
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Description: altera 的示例ip,不太容易找到的,对于学习Nios2有帮助
Platform: |
Size: 14057 |
Author: 林茂 |
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Description: altera 的sina函数ip核,可直接调用
Platform: |
Size: 1997 |
Author: 李涛 |
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Description: altera 的cosine函数 ip 核
Platform: |
Size: 2374 |
Author: 李涛 |
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Description: altera 的i2c ip核,可直接调用
在quartus中把库指向文件位置就可
Platform: |
Size: 7645 |
Author: 李涛 |
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Description: altera 的uart ip核,可直接调用
在quartus中把库指向文件位置就可
Platform: |
Size: 5060 |
Author: 李涛 |
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Description: 利用Altera的IP核,实现FFT算法使用信息流模式读写,使用SignalTap II嵌入式逻辑分析仪观察信号,A/D只要是并行的8位芯片都可以。-Achiving FFT by using Altera IP Core,you can observe the signal by the embedded logic analyzer Signal Tap II,as for A/D device, it s suitable for a parllarel 8 bits A/D device.
Platform: |
Size: 22096896 |
Author: 常泽文 |
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Description: 区别于altera官方的frame reader,完全自定义设计(Different from the official frame reader of Altera, fully custom design)
Platform: |
Size: 473088 |
Author: 奎木狼
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Description: 基于Altera 的一个IP核,能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
Platform: |
Size: 19784704 |
Author: 机智的伟哥哥 |
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Description: 使用altera提供的ip核,实现了浮点数运算的2阶iir滤波器,结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
Platform: |
Size: 48926720 |
Author: 小天夫斯基 |
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